Skip to main content

Device Integration Engineer

קריית גת, ישראל Job ID JR0247851 Job Category Manufacturing and Process Development Work Mode Hybrid Experience Level Experienced

Job Description

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany.

As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in high-volume manufacturing at a 2-year cadence going forward.

Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This job requisition is to seek Device Integration engineering roles in FSM HVM Global Yield organization, reporting to Manager/Director of Device Integration Engineering.

Selected candidates will work with other members in Global Yield org including Process Integration, Yield Analysis and Defect engineering teams, fab module/yield teams and TD team members to achieve yield ramp-up and process optimization in early production stage, supporting internal and external customers.

Device Integration engineers' responsibilities include (but are not limited to):

  • Own engineering projects to execute HVM yield roadmap, device targeting and attain performance targets.
  • Work with Technology Development team to develop new device technology, customize device architecture per customer request and import to production fabs.
  • Participate or lead cross-organizational team of engineers to identify root cause of device-related yield/performance issues and define mitigation plan to meet committed production yield/performance targets.
  • Own NPI (New Product Introduction) in production fab and perform device-related process optimizations to meet foundry customers product specifications and requirements.
  • Develop a model to predict device performance accurately in early-to-mid stage of Si progression and drive systematic solution to maintain baseline device performance.
  • Work with Process Integration engineers to drive process simplification and implement cost reduction engineering opportunities in line.
  • Level of experience will be considered in determining applicants job grade.

Candidate should possess the following behavioral skills:

  • Problem-solving technique with strong self-initiative and self-learning capabilities.
  • Ability to work with multi-functional, multi-cultural teams.
  • Must demonstrate solid communication skills.


Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Bachelor's degree in Electrical Engineering, Physics or Materials Science major. Other related science and engineering degrees can be considered based on industry experience.
  • 3+ years' experience in advanced node semiconductor industry in Device Integration.
  • 3+ years' experience in FinFET technology development or high-volume manufacturing.
  • 3+ years' experience with Device Physics and hands-on application in real-world fab environment.
  • 3+ years' experience with FEOL (Front-End-Of-Line) Integration teams including Fin, Poly, Source-Drain and Gate segments on Device performance improvement and targeting with technical understanding on how FEOL process changes impact Device parameters.

    Preferred Qualifications:
  • Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics or Materials Science major.
  • Experience in project/program management and/or TFT lead.
  • Demonstrated interpersonal skills including influencing, engaging, and motivating.
  • Experience in serving external Foundry customers through technical interactions.
  • Experience in GAA (Gate-All-Around) technology architecture.
  • Experience in new semiconductor technology development.
  • Basic understanding and collaboration experience with module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.


Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

לא נצפו משרות לאחרונה.

לצפייה בכל המשרות

לא נצפו משרות לאחרונה.

לצפייה בכל המשרות