Electronic-Photonics Software Tools Engineer

Job Description

Intel Integrated Photonics Solutions (IPS) is at the forefront of silicon photonics integration and commercialization. Since announcing the world's first hybrid silicon laser nearly a decade ago, our team continues to lead the industry with cutting-edge technology and efficient, scalable high-volume manufacturing. Our dedication to advanced development ensures that Intel Silicon Photonics continues to drive future data center and advanced AI datacenter bandwidth growth with smaller form factors, co-packaging and higher speeds. We are looking for great talent to accelerate this journey so if you are interested in joining our leading organization then we want to hear from you. 

We are seeking a senior Electronic-Photonic Software Tools engineer for developing Photonics Design tools, flows, methods (TFM) with extensive industry experience and a track record enabling complex design tape out's and successfully taking the designs to market. Key Responsibilities include developing and deploying TFM for high-speed, analog mixed-signal Photonic IC designs from concept to high volume. As one of the Physical Verification experts in the team, you will be expected to assume a leadership role in enabling design rule deck and LVS run sets for multiple customers and partners (Internal and/or External) using industry standard EDA software such as Cadence, Mentor, Synopsys, etc.

Work Model for this Role:This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Relocation assistance provided.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

The candidate must have a Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, Applied Physics, Optical Physics, Optical Communications, Optical Science or related field.

8+ years of experience in Electronic Design Automation Software Development focused on Physical Verification, Layout verification, and/or run set development

3+ years of combined experience in the following:

• Development of foundry rule deck (DRC and LVS) runsets
• Expertise in industry standard integrated circuits (IC) design CAD tools/flows such as Siemens Calibre, Cadence Virtuoso
• Software development/programming in high-level languages (e.g. Perl/Python/ Shell/TCL/C++).
• Scripting and SKILL coding, Calibre SVRF/TVF and Synopsys ICValidator
• Analog IC or Photonic Integrated Circuit (PIC) design concepts and flows

Preferred Qualifications:

• MS with 6+ years /Ph.D with 4+ years of experience in Electronic Design Automation Software Development focused on Physical Verification, Layout verification, and runset development
• Developing Smart Fill decks, DRC/LVS runset development, parasitic extraction and support in EDA tools and flows such as Synopsys ICV, Siemens/Mentor Calibre, Cadence PVS/Pegasus
• Familiarity with Virtuoso Photonic Solutions, including hands-on experience scripting in SKILL and using Virtuoso CurvyCore concepts and implementation.
• Experience with Synopsys OptoCompiler including the ability to design and implement photonic components and circuits using these tools; Proficiency in coding and scripting for Synopsys IC Validator (ICV) to perform design rule checks (DRC) and layout versus schematic (LVS) verification
• Versatile in Design Tools, flows and Methods, broad expertise with Pcells, Schematic Driven Layout (SDL), Floor planning, Infrastructure and Environment set up and version control
• Experience in VLSI circuit, CMOS layout design and validation
• Experience with multiple foundry technologies
• Experience using Unix or Linux operating system
• Test case generation automatic & manual, QA and validation
• Graduate degree in Photonics and/or expertise in Photonic IC (PIC) design, design automation will be a definite plus
• Excellent people skills with an ability to influence stakeholders and lead cross functional team of Layout engineers, designers, design automation and fab process integrators
• Expert technical problem solver with hands on execution experience with TI, TO process for complex hierarchical designs

Inside this Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Other Locations

US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Folsom

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in the US $196,830.00-$277,880.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.