Failure Analysis and Fault Isolation (FA/FI) Manager

Job Description

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany.

Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development (TD) team, and FSM fab managers.

This job requisition is seeking a Failure Analysis & Fault Isolation (FA/FI) Group Leader working in our Arizona Global Yield Development Laboratory which operates 24/7.  Selected candidate will manage a team of FI/FA engineers supporting both electrical and physical failure analysis (EFA / PFA) activities.  Team works closely with Yield Analysis team members to identify root cause of failures enabling yield ramp-up and process optimization in early production stage, supporting both internal and external customers.

FI/FA Group Leader’s responsibilities include (but are not limited to):

• Nurture, grow & lead newly formed team, responsible for team health and people management, including hiring, technical coaching, skill development, training, and performance management.

• Review team’s work and ensure technical accuracy, provide guidance and recommendations on approaches to characterize complex analyses.

• Deliver world class operational performance in safety, quality, and lab throughput along with tactical management of area.

• Understand area workflows and equipment, help manage tool fleet including optimizing area to increase output & reduce tool down time.

• Present results of key analyses to internal and external customers.

Candidate should have the following behavioral skills:

• Demonstrated strength in leadership, teamwork, problem solving, and effective oral and written communication skills.

• Desire to learn and expand knowledge in field.

• Ability to work with multi-functional, multi-cultural teams.

• Strong in decision making and problem solving.

• A good motivator, with ability to listen.

Qualifications

Minimum Qualifications:

• Bachelor's degree in science and engineering major.

• 4+ years' experience in a semiconductor failure analysis laboratory.

Preferred Qualifications:

• Advanced degree (Master's or Ph.D.) in science and engineering major.

• 10+ years’ experience in a semiconductor failure analysis laboratory supporting advanced technology node technology development.

• Strong understanding of TEM sample preparation and imaging.

• 4+ years’ experience with 6T SRAM & logic failure analysis.

• Strong technical understanding of modern fault isolation & failure analysis techniques, from fault isolation, nanoprobing through physical analysis.

• Understanding of FinFET technology architecture, including Cu metallization.

• Basic understanding on fabrication processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in the US $105,797.00-$175,105.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.