Physical Design Engineer

Job Description

In this position, you will participate in our Test Chip design execution, validate and deliver a robust, fully validated reference design and sign off flows, in partnership with EDA vendors and other Intel Foundry partner organizations. You will involve in building the design using the foundry reference flows and continuously improve/update the design to exercise/stretch the flows in various metrics that matter most to our customers. You will help create documentation/trainings to bring our customers up-to-speed in using these flows along with Intel PDK collaterals. In addition, our team drives Intel Foundry technologies and solutions into our customer's engineering teams and is the customer advocate with internal development teams. You will ensure Intel collaterals and services can continuously meet customers' needs that would lead to successful chip tape-outs. Joining this group means you will be representing Intel in enabling customers' satisfying experiences and eventual outcome, financial success. You will have an opportunity to grow and expand your knowledge on various ASIC physical design domains and will be exposed to various challenges that customers encounter. In this role you may: - validate the overall Foundry design platform based on vendor reference flows - execute internal Test Chip design, including 3DIC related Test Chips - create and deliver customer training and application notes - provide technical support to customers - collaborate with internal teams and EDA vendors on issue resolution - develop methodology and automation to improve design productivity and efficiency - PDK and design collaterals validation, to name a few. #DesignEnablement

Qualifications

Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 1 years of experience in SOC/Analog/IP/ASIC design and/or methodology development. Preferred Qualifications: - Minimum 1 years of experience in writing and producing software code using languages such as PERL and TCL. - Minimum 1 years of experience in running Synthesis, Place and Route physical design tools and flow, with demonstrated expertise in design constraints and optimization, timing convergence, low power checks, IR drop analysis and fixes, layout DRC analysis andd fixes, and successful tape-out of designs in advanced nodes. - Experience in Unix/Linux and shell programming. - Experience in 3DIC design will be an added advantage.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.